CMP (Chemical Mechanical Planarization) and dry etching processes widely used in semiconductor integrated circuits manufacturing may cause variations in profiles and patterns of the chips, and therefore may reduce the yield of chips and influence the performance of chips. Thus, it is a common practice that a dummy pattern insertion method be adopted in the CMP and dry etching processes to improve the profiles and patterns of the chips so as to improve within-wafe uniformity.
The most popular dummy pattern insertion method used in the prior art includes the following steps: first, an applicable area in which dummy patterns shall be inserted on a wafer surface is determined based on the relationships between multiple layers of a device. Then dummy patterns are inserted into this applicable area starting from an endpoint of one boundary of the applicable area. The step of inserting dummy patterns continues until the opposite boundary of the applicable area is reached. This method may be affected by the initial position of the first dummy pattern that is inserted. When an inappropriate initial position is selected, the method of inserting dummy patterns may not be carried out successfully. An example will be given as follows.
As shown in FIG. 1, a dummy pattern F is in the shape of a square with a side length of a, and the interval between two dummy patterns is b. A chip D as shown in FIG. 2 may include an inapplicable area B in which dummy patterns shall not be inserted and an applicable area C in which dummy patterns shall be inserted. In this example, the distance between the upper boundary of the inapplicable area B and the upper boundary of the chip D is 2a+b, which is just enough for two dummy patterns F to be inserted. However, whether or not two dummy patterns F can be actually inserted is determined by the initial position of the first dummy pattern to be inserted.
For example, if the initial position A is selected as the left upper corner of the applicable area C, as shown in FIG. 3, two dummy patterns F can be successfully inserted along the vertical direction between the upper boundaries of the inapplicable area B and the chip D. Otherwise, if the initial position A is selected as the left lower corner of the applicable area C, as shown in FIG. 4, problem may arise that two dummy patterns F cannot be successfully inserted along the vertical direction between the upper boundaries of the inapplicable area B and the chip D, leading to failure of inserting dummy patterns at certain areas where dummy patterns are required by the device. In FIG. 3 and FIG. 4, dummy patterns F′ that are partly or entirely formed in the inapplicable area B will be removed.
With the increase of the demands on miniaturization and yield of semiconductor devices, the higher and higher within-wafer uniformity is being required. The above dummy pattern insertion method can no longer meet the requirements of the process.